Samsung details new 65/14nm stacked sensor design for improving power efficiency, density of mobile image sensors: Digital Photography Review

Stacked Architecture of the chipset Samsung details in its new paper.

Samsung has published a paper detailing a new stacked CMOS mobile image sensor that uses a 14nm processing layer to deliver high-resolution images while reducing power consumption.
The stacked sensor consists of two chips: a 12MP backside-illuminated (BSI) pixel chip on the top that uses 65nm process and a bottom chip for analog and logic circuits that uses 14nm process. By using the super-fine 14nm process on the processing layer, Samsung says it could achieve a 29% drop in power consumption compared to current conventional sensors that use a 65nm/28nm process.

Microphotograph of Implemented Sensor (Left: Top Chip & Right: Bottom Chip)

Samsung says the chip is capable of outputting at 120 frames…

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